1. Field of the Invention
This invention relates to the field of buffer circuits capable of modifying the propagation delays of rising and falling edges propagating through a signal path.
2. Description of the Related Art
Automatic test equipment (ATE) is often used to test electronic circuitry. This is done by applying a variety of stimuli to a device to be tested, referred to herein as a xe2x80x9cdevice-under-testxe2x80x9d (DUT), and monitoring the DUT""s responses.
The stimuli takes the form of test signals having predefined characteristics, which are applied to the DUT in a predetermined manner. A typical ATE system is shown in FIG. 1. A pattern generator 10 stores digital information representing the characteristics, such as duty cycle, frequency, amplitude, etc., of the test signals to be provided to a DUT 12. This information is provided to a timing vernier 14, which generates signal edges and/or pulses in accordance with the digital information. These are passed onto a formatter, which combines the edges and pulses into the desired waveforms.
The formatter output is typically provided to a xe2x80x9cpin electronics ICxe2x80x9d 18, which provides an interface between the ATE and the DUT. The pin electronics IC includes one or more driver circuits 20, which enable the test signals to be applied to the DUT at the voltage and current levels required by the device. IC 18 also typically includes one or more comparator circuits 22, which are used to monitor respective DUT outputs.
Unfortunately, errors may be introduced into the test signals as they propagate through the ATE system. For example, rising and falling edges may be delayed by different amounts as they propagate through the ATE. As used herein, the propagation delay of a test signal""s rising edge through a given signal path is referred to herein as xe2x80x9cTPDLHxe2x80x9d (total propagation delay low-to-high), and the propagation delay of its falling edge is referred to as xe2x80x9cTPDHLxe2x80x9d (total propagation delay high-to-low). When TPDLH and TPDHL are unequal, pulse width and/or duty cycle errors arise in the test signals actually applied to the DUT 12. Discrepancies between TPDLH and TPDHL values can be induced by the signal path through which the test signal propagates, due to imperfections or mismatches in IC 18, its preceding circuits, and/or its following circuits; such errors are referred to herein as xe2x80x9csignal path errorsxe2x80x9d. The TPDLH and TPDHL values can also be adversely affected by thermal effects that arise when propagating a periodic test signal having a duty cycle other than 50% through the signal path, due to the unequal heating of transistors in the signal path; errors of this type are referred to herein as xe2x80x9ctemperature-related errorsxe2x80x9d.
A buffer circuit and method are presented which overcome the problems noted above, reducing both signal path and temperature-related errors in many timing-critical applications. The invention is particularly well-suited for use in ATE systems as described above.
The buffer circuit includes a delay circuit which is interposed between a signal source and a following circuit. For example, in an ATE system, the delay circuit may be interposed between the output of an ATE system""s formatter and its drivers. The delay circuit propagates a signal from an input to an output; the signal has associated desired timing relationships between its rising and falling edges. The delay circuit adjusts the propagation delays of the signal""s rising and falling edges such that when the signal has propagated to a selected downstream node, it has the desired timing relationships. For example, in an ATE system, the test signals applied to a DUT might be monitored for duty cycle errors, and the delay circuit arranged to adjust the propagation delay of the test signals"" rising and falling edges such that the duty cycle errors detected at the DUT are reduced.
In a preferred embodiment, the buffer circuit receives signals having true and complement forms, and produces true and complement outputs. The received signals are connected to a first differential transistor pair, with the true and complement signals propagated to the output via a second differential transistor pair and an output stage. The rising and falling edge propagation delays are adjusted by means of a clamp circuit connected to the second pair""s inputs which controls the voltage swing at each input. Respective capacitors are also connected to the second pair""s inputs, each of which linearizes the slope of a transitioning signal and extends the propagation delay adjustment range.
The clamp circuit establishes the voltage swingsxe2x80x94and thereby the propagation delaysxe2x80x94in accordance with two correction signals: one to reduce signal path errors, and one to reduce temperature-related errors. Signal path errors are detected by monitoring the timing relationships between the propagating signal""s rising and falling edges at the selected downstream node under controlled conditions. The signal path error correction signal is generated to reduce the error detected at the downstream node.
Temperature-related errors vary with the desired duty cycle of a propagating signal which is periodic. Therefore, the temperature-related error correction signal is generated by detecting the signal""s desired duty cycle, and varying the correction signal in accordance with the detected duty cycle.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.